With a common gate (GREF) and a reference transistor (SREF and DREF), the GTL2003 provides eight NMOS pass transistors (Sn and Dn) and allows bidirectional voltage translations between 0.8 V and 5.0 V without use of a direction pin. When properly biased, voltage translation below 0.8 V can be achieved.
All transistors have the same electrical characteristics and there is minimal deviation from one output to another in voltage or propagation delay. This is a benefit over discrete transistor voltage translation solutions, since the fabrication of the transistors is symmetrical. Because all transistors in the device are identical, SREF and DREF can be located on any of the other eight matched Sn/Dn transistors, allowing for easier board layout.
- Allows voltage level translation between 0.8 V, 0.9 V, 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5 V buses which allows direct interface with GTL, GTL+, LVTTL/TTL and 5 V CMOS levels
- Supports hot insertion
- No power supply required: will not latch up
- ESD protection exceeds 2000 V HBM per JESD22-A114, and 1000 V CDM per JESD22-C101
- Any application that requires bidirectional or unidirectional voltage level translation from any voltage from 0.8 V to 5.0 V to any voltage from 0.8 V to 5.0 V
- The open-drain construction with no direction pin is ideal for bidirectional low voltage (for example, 0.8 V, 0.9 V, 1.0 V, 1.2 V, 1.5 V, or 1.8 V) processor I²C-bus port translation to the normal 3.3 V and/or 5.0 V I²C-bus signal levels or GTL/GTL+ translation to LVTTL/TTL signal levels.