Monthly Archives: November 2017

3-Channel Multipoint Fast-mode Plus Differential I²C-bus Buffer with Hot-Swap Logic

PCA9616PW Block Diagram

PCA9616PW Block Diagram

This PCA9616PW IC consists of three single-ended to differential drive channels for the SCL (serial clock), SDA (serial data), and a third channel useful for INT or other signaling. It features the new dI²C-bus buffers that improved resistance to system noise and ground offset up to 1/2 of supply voltage.

PCA9616PW Fast-mode Plus (Fm+) SMBus/I²C-bus buffer that extends the normal single-ended SMBus/I²C-bus through electrically noisy environments using a differential SMBus/I²C-bus (dI²C) physical layer, which is transparent to the SMBus/I²C-bus protocol layer.

This device is a bridge between the normal 2-wire single-ended wired-OR SMBus/I²C-bus and the 4-wire dI²C-bus. Additional circuitry allows the PCA9616 to be used for ‘hot swap’ applications, where systems are always on, but require insertion or removal of modules or cards without disruption to existing signals.

Why Used

  • Hot swap (allows insertion or removal of modules or card without disruption to bus data)
  • New dI²C-bus buffers offer improved resistance to system noise and ground offset up to 1⁄2 of supply voltage
  • Bus idle detect (PCA9616 internal function) waits for a bus idle condition before connection is made
  • 3 channel dI²C (differential I²C-bus) to Fm+ single-ended buffer operating up to 1 MHz with 30 mA SDA/SCL > 2.2 V, or 3 mA SDA/SCL < 2.4 V
  • Compatible with I²C-bus Standard/Fast-mode and Fast-mode Plus at 1 MHz

Where Used

  • Any application that requires long I²C-bus runs in electrically noisy environments
  • Monitor remote temperature/leak detectors in harsh environment with interrupt back to master
  • Control of power supplies in high noise environment
  • Transmission of I²C-bus between equipment cabinets
  • Any application with multiple power supplies and the potential for ground offsets up to 2.5 V

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Dual High-Speed USB 2.0 Double-Pole Double-Throw Analog Switch

NX3DV42 Logic Diagram

NX3DV42 Logic Diagram

Dual high-speed USB 2.0 double-pole double-throw analog switch is the NX3DV42 IC with a wide bandwidth in which it is enough to pass high-speed USB 2.0 differential signals (480 Mb/s). This device features a 960 MHz typical bandwidth or data frequency and low crosstalk of -30 dB at 240 MHz.

Its wide bandwidth and low bit-to-bit skew allows the NX3DV42 to pass high-speed differential signals with good signal integrity. Its high channel to channel crosstalk rejection results in minimal noise interference. NX3DV42 consist of two switches, each with two independent input/outputs (HSDn+ and HSDn-) and a common input/output (D+ or D-). One digital inputs (S) is used to select the switch position. When pin OE is HIGH, the switches are turned off. Schmitt trigger action at the select input (S) and enable input (OE) makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 3.0 V to 4.3 V.

Why Used

  • 4 Ω typical ON resistance
  • 7.3 pF typical ON capacitance
  • 50 MHz typical bandwidth or data frequency
  • Low crosstalk of -30 dB at 240 MHz
  • Supply voltage range from 3.0 V to 4.3 V

Where Used

  • LCD monitor, TV and set-top box
  • Cell phone, PDA, Digital camera and notebook

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Dual Double-Pole Double-Throw Analog Switch

NX3DV3899 Logic Diagram

NX3DV3899 Logic Diagram

The NX3DV3899 analog switch IC consists of four switches, each with two independent input/outputs (nY0 and nY1) and a common input/output (nZ). It features a break-before-make switching and latch-up performance exceeds 100 mA per JESD 78B Class II Level A.

This dual double-pole double-throw analog data-switch device has wide supply voltage range from 1.4 V to 4.3 V. There are two digital inputs (1S and 2S) used to select the switch position. A schmitt trigger action at the select input (nS) makes the circuit tolerant to slower input rise and fall times across the entire  VCC range from 1.4 V to 4.3 V. Low input voltage threshold allows pin nS to be driven by lower level logic signals without a significant increase in supply current ICC. This makes it possible for the NX3DV3899 to switch 4.3 V signals with a 1.8 V digital controller, eliminating the need for logic level translation.

The NX3DV3899 dual double-pole double-throw analog data-switch IC is suitable for use as an analog or digital multiplexer/demultiplexer.

Why Used

  • Very low ON resistance (peak):
    • 7.2 Ω (typical) at VCC = 1.4 V
    • 5.4 Ω (typical) at VCC = 1.65 V
    • 2.9 Ω (typical) at VCC = 2.5 V
    • 2.4 Ω (typical) at VCC = 3.0 V
    • 2.3 Ω (typical) at VCC = 3.6 V
    • 2.2 Ω (typical) at VCC = 4.3 V
  • ESD protection:
    • HBM JESD22-A114F Class 2A exceeds 2000 V (all pins)
    • HBM JESD22-A114F Class 3A exceeds 5000 V (I/O pins to GND)
    • MM JESD22-A115-A exceeds 200 V
    • CDM AEC-Q100-011 revision B exceeds 1000 V
  • Wide supply voltage range from 1.4 V to 4.3 V
  • High noise immunity
  • 1.8 V control logic at VCC = 3.6 V

Where Used

  • Data switch
  • Cell phone
  • PDA
  • Portable media player

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2-Channel Multipoint Fast-mode Plus Differential I2C-bus Buffer with Hot-Swap Logic

PCA9615 Block Diagram

PCA9615 Block Diagram

The PCA9615 IC is a 2-channel multipoint fast-mode plus differential I2C-bus buffer with hot-swap logic that consist of two single-ended to differential driver channels for the SCL (serial clock) and SDA (serial data). It is a fast-mode plus (Fm+) SMBus/I2C-bus buffer that extends the normal single-ended SMBus/I2C-bus through electrically noisy environments using a differential SMBus/I2C-bus protocol layer.

The use of differential transmission lines between identical dI2C bus buffers removes electrical noise and common-mode offsets that are present when signal lines must pass between different voltage domains, are bundled with hostile signals, or run adjacent to electrical noise sources, such as high energy power supplies and electric motors.

This device is a bridge between the normal 2-wire single ended wired-OR SMBus/I2C and the 4-wire dI2C-bus.

Why Used

  • 2 channel dI²C (differential I²C-bus) to Fm+ single-ended buffer operating up to 1 MHz with 30 mA SDA/SCL drive capability
  • Hot swap (allows insertion or removal of modules or card without disruption to bus data)
  • New dI²C-bus buffers offer improved resistance to system noise and ground offset up to 1⁄2 of supply voltage
  • EN signal (PCA9615 input) controls PCA9615 hot swap sequence
  • Bus idle detect (PCA9615 internal function) waits for a bus idle condition before connection is made

Where Used

  • Transmission of I²C-bus between equipment cabinets
  • Commercial lighting and industrial heating/cooling control
  • Any application that requires long I²C-bus runs in electrically noisy environments
  • Monitor remote temperature/leak detectors in harsh environment
  • Control of power supplies in high noise environment

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