Monthly Archives: October 2017

Single-Port TCPC Compliant USB Power Delivery (PD) PHY IC

PTN5100 Block Diagram

PTN5100 Block Diagram

The PTN5110 IC targeted primarily for use in system platforms (e.g. Notebook PCs, Desktop PCs, Chromebooks, Tablets, Convertible, etc.). It implements Type-C Configuration Channel (CC) interface and USB PD Physical layer functions to a type-C Port Manager (TCPM) that handles PD Policy management. It is designed to comply with USB PD, Type-C and TCPC specifications. Other use cases may be feasible depending on the application architecture, e.g. docks, monitors, accessories, cable adapters, smartphones etc.

It can support various type-C roles: Sink, Source, Sink with accessory support or DRP. It implements Type-C CC analog portion (i.e Rd/Rp/Ra detection, Rd/Rp indication) and PD Tx/Rx PHY and protocol state machines. PTN5110 supports TCPM in system realization of the following PD roles:

  • Provider (P)
  • Provider/Consumer (P/C)
  • Consumer (C)
  • Consumer/Provider (C/P)

Why Used

  • Provides the majority of relevant IO capability for the host processor/TCPM to easily control and manage the Type-C/PD interface via the TCPC interface
  • Offers tremendous flexibility to platform integrators by supporting a wide range of power supply input voltages
  • Available in HX2QFN16, 2.6 mm x 2.6 mm x 0.35 mm, 0.4 mm pitch

Where Used

  • PC platforms: Notebook PCs, Desktop PCs, Ultrabooks, Chromebooks
  • Tablets, 2:1 Convertibles, Smartphones and Portable devices
  • PC accessories/peripherals: Docking, Mobile Monitors, Multi-Function Monitors, Portable/External hard drives, Cable adaptors, Dongles and accessories, etc.

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18 V tolerant SPI 16-bit/8-bit GPI with INT

 

PCA9701/PCA9702 Block Diagram

PCA9701/PCA9702 Block Diagram

PCA9701/PCA9702 are SPI General Purpose Input (GPI) shift registers that generates an interrupt when one or more of the switch inputs change state. It is designed to monitor the status of switch inputs. The input level is recognized as a high when it is greater than 0.7 x VDD and as a LOW when it is less than 0.4 x VDD (minimum threshold of 2 V at 5 V node).

The PCA9701 can monitor up to 16 switch inputs and the PCA9702 can monitor up to 8 switch inputs. Each of the input ports has a 18 V breakdown ESD protection circuit. When used with a series resistor (minimum 100kΩ), the input can connect to a 12 V battery and support double battery, reverse battery, 27 V jump start and 40 V load dump conditions in automotive applications. Higher voltages can be tolerated on the inputs depending on the series resistor used to limit the input current.

Why Used

  • VDD rangeL 2.5 V to 5.5 V
  • IDD is very low 2.5 uA maximum
  • SPI serial interface with speeds up to 5MHz
  • 16 general purpose input ports (PCA8701) or 8 general purpose input ports (PCA9702)
  • 18 V tolerant input ports with 100 kΩ external series resistor

Where Used

  • Switching Monitoring
  • Industrial equipment
  • Body control modules
  • Cellular telephones
  • Emergency lighting

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2-channel I2C-Bus Master Arbiter

Block Diagram of PCA9641

Block Diagram of PCA9641

A 2-channel I2C-bus master arbiter IC is a 2-to-1 I2C master demultiplexer with an arbiter function device, which is the PCA9641. This PCA9641 is designed for high reliability dual master I2C-bus applications where correct system operation is required, even when two I2C-bus masters issue commands at the same time.

The arbiter will select a winner and let it work uninterrupted, and the losing master will take control of the I2C-bus after the winner has finished. The arbiter also allows for queued requrests where a master requests the downstream bus while the other master has control.

Why Used

  • Channel selection via I2C-bus
  • Arbitration active when two masters try to take the downstream I2C-bus at the same time
  • 2 active LOW interrupt outputs to master controllers
  • Four address pins allowing up to 112 different addresses
  • The winning master controls the downstream bus until it is done, as long as it is within the reserve time

Where Used

  • High reliability systems with dual masters
  • Gatekeeper multiplexer on long single bus
  • Bus initialization/recovery for slave devices without hardware reset
  • Allow masters without arbitration logic to share resources

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USB PD TCPC PHY IC

Block diagram of PCA9514A

Block diagram of PCA9514A

PCA9513A and PCA9514A are how swappable I2C-bus and SMBus bus buffer ICs that is compatible with I2C-bus standard mode, I2C-bus Fast mode, and SMBus standards. It allow I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus contention on the card. When the connection is made, the PCA9513A and the PCA9514A provides bidirectional buffering, keeping the backplane and card capacitances isolated.

Why Used

  • Built-in ΔV/Δt rise time accelerators on all SDA and SCL lines (0.8 V threshold) requires the bus pull-up voltage and supply voltage (VCC) to be the same
  • Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and SCL corruption during live board insertion and removal from multipoint backplane systems.
  • Rise time accelerator threshold moved from 0.6 V to 0.8 V for improved noise margin
  • Active HIGH ENABLE input
  • Active HIGH READY open-drain output

Where Used

  • cPCI, VME, Advanced TCA cards and other multipoint backplane cards that are required to tbe inserted or removed from an operating system.

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Dual Supply Translating Transceiver; Open Drain; Auto Direction Sensing

 

NTS0103GU10 Logic Symbol Functional Diagram

NTS0103GU10 Logic Symbol Functional Diagram

NTS0103 is one of the voltage translator device of NXP, which is a 3-bit, dual supply translating transceiver with auto direction sensing that enables bidirectional voltage level translation. This device features two 3-bit input-output ports (An and Bn), one output enable input (OE) and two supply pins (VCC(A) and VCC(B)). VCC(A) can be supplied at any voltage between 1.65 V and 3.6V and VCC(B) can be supplied at any voltage between 2.3 V and 5.5 V, making the device suitable for translating between any of the voltage nodes (1.8 V, 2.5 V, 3.3 V, and 5.0 V). Pins An and OE are referenced to VCC(A) and pins Bn are referenced to VCC(A) and pins Bn are referenceed to VCC(B). A LOW level at pin OE causes the outputs to assume a high-impedance OFF-state. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Why Used

  • Maximum data rates:
    • Push-pull: 50 Mbps
  • Latch-up performance exceeds 100 mA per JESD 78BB Class II
  • Wide supply voltage range:
    • VCC(A): 1.65 V to 3.6 V and VCC(B): 2.3 V to 5.5 V
  • Inputs accept voltages up to 5.5 V
  • ESD protection:
    • HBM JESD22-A114E Class 2 exceeds 2500 V for A port
    • HBM JESD22-A114E Class 3B exceeds 8000 V for B port
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101E exceeds 1500 V
    • IEC61000-4-2 contact discharge exceeds 8000 V for B port

Where Used

  • UART
  • I²C/SMBus
  • GPIO

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