Monthly Archives: August 2017

PCF85363A Tiny Real-Time Clock/Calendar

This PCF85363A Real-Time Clock/calendar (RTC) IC is used provide date and time while having some extra features as RTC. It is a RTC/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input, and I2C-bus. This device is optimized low power consumption and with automatic switching to battery on main power loss. The RTC can also be configured as a stop-watch (elapsed time counter). Three time log registers triggered from battery switch-over as well as input driven events.

PCF85363A Block Diagram

Block Diagram

Why Used

  • Two independent alarms
  • Two independent interrupt generators plus predefined interrupts at every second, minute, or hour
  • UL Recognized Component (PCF85363ATL)
  • Battery Back-up Circuit
  • Frequency adjustment via programmable offset register

Where Used

  • Network powered devices
  • Printers and copiers
  • Digital voice recorders
  • Mobile equipment
  • Elapsed time counter

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PCF8579 LCD Column Driver for Dot Matrix Graphic Displays

PCF879 forms part of a chip capable of driving up to 40960 dots used in conjunction with the PCF8578 LCD row/column driver. The PCF8579 is a low power CMOS LCD column driver, designed to drive dot matrix graphic displays at multiplex rates of 1:8, 1:16, 1:24 or 1:32. The device has 40 outputs and can drive 32 x 40 dots in a 32 row multiplexed LCD. Up to 16 PCF8579 can be cascaded and up to 32 devices may be used on the same I²C-bus (using the two slave addresses). Together these devices form a general purpose LCD dot matrix driver chip set, capable of driving displays of up to 40960 dots. The PCF8579 is compatible with most microcontrollers and communicates via a two-line bidirectional bus (I²C-bus). To allow partial VDD shutdown the ESD protection system of the SCL and SDA pins does not use a diode connected to VDD. Communication overhead is minimized by a display RAM with auto-incremented addressing and display bank switching.

Block Diagram

Block Diagram

Why Used

  • 1280-bit RAM for display data storage
  • 40 column outputs
  • LDC column driver
  • Selectable multiplex rate multiplex; 1:8, 1:16, 1:24 or 1:32
  • Externally selectable bias configuration, 5 or 6 levels

Where Used

  • Point-of-Sales (PoS) terminals
  • Industrial computer terminals
  • Automotive information systems
  • Telecommunication systems
  • Instrumentation

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Universal LCD Driver for Low Multiplex Rates including a 6 channel PWM Generator

Featuring as a single-chip 320 segment LCD controller and driver with 6 channel PWM generator, the PCF8536 IC is compatible with most microcontrollers and communicates via the two-line bidirectional I²C-bus (PCF8536AT) or a three line unidirectional SPI-bus (PCF8536BT). It is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex LCD containing up to eight backplanes, up to 44 segments, and up to 320 elements. Communication overheads are minimized using a display RAM with auto-incremented addressing.

Block Diagram

Block Diagram

Why Used

  • 6 channel PWM generator for backlight LED illumination
  • Wide range for digital power supply: from 1.8 V to 5.5 V
  • Wide LCD supply range: from 2.5 V for low threshold LCDs and up to 9.0 V for high threshold twisted nematic LCDs
  • Selectable display bias configuration
  • Low power consumption
  • Selectable backplane drive configuration: 4, 6, or 8 backplane multiplexing

Where Used

  • Manufactured in silicon gate CMOS process

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Dual Bidirectional Bus Buffer

PCA9601 IC is a high-speed version of P82B96 that is designed to isolate I²C-bus capacitance. It allows greater than 400 pF on SX/SY side and 4000 pF on TX/TY side. It is also a higher version of the PCA9600 that allows many more Fast-mode Plus (Fm+) slaves on remote daughter cards in applications with temperature range of 0°C. It can operate at speeds up to at least 1 MHz, and the high drive side is compatible with the Fast-mode Plus specifications.

The PCA9601 features temperature-stabilized logic voltage level at its SX/SY interface making it suitable for interfacing with buses that have non I²C-bus-compliant logic levels such as SMBus, PMBus, or with microprocessors that use those same TTL logic levels.

The separation of the bidirectional I²C-bus signals into unidirectional TX and RX signals enables the SDA and SCL signal to be transmitted via balanced transmission lines (twisted pairs), or with galvanic isolation using opto or magnetic coupling. The TX and RX signals may be connected together to provide a normal bidirectional signal.

Block Diagram

Block Diagram

Why Used

  • Supply voltage range of 2.5 V to 15 V with I²C-bus logic levels on SX/SY side independent of supply voltage
  • 15 mA SX/SY sink capability yields 5 V Fm+ bus rise time with 470 pF loads
  • 1 MHz operation on up to 20 meters of wire (see AN10658)
  • Splits I²C-bus signal into pairs of forward/reverse TX/RX, TY/RY signals for interface with opto-electrical isolators and similar devices that need unidirectional input and output signal paths
  • Low power supply current

Where Used

  • Simple conversion of I²C-bus SDA or SCL signals to multi-drop differential bus hardware, for example, via compatible PCA82C250
  • Interfaces with opto-couplers to provide opto-isolation between I²C-bus nodes up to 1 MHz
  • Long distance point-to-point or multipoint architectures
  • Interface between I²C-buses operating at different logic levels (for example, 5 V and 3 V or 15 V)
  • Interface between I²C-bus and SMBus (350 μA) standard or Fm+ standard

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