Monthly Archives: January 2017

USB Type-C PD PHY and protocol IC, SPI for dongles

Complying with USB PD and Type-C specifications, PTN5100D is a single port USB Type-C Power Delivery PD (PD) PHY and Protocol IC that provides Type-C Configuration channel interface and USB PD Physical and Protocol layer functions to a System PD Port Policy Controller. PTN5100D can support system realization of the following PD roles: (i) Consumer only (ii) Consumer/Provider.

PTN5100D is architected to deliver robust performance, compliant behavior, configurability and system implementation flexibility that are essential to tide over interoperability and compliance hurdles in the platform applications. PTN5100D is available in a small footprint package option: HVQFN20 4 mm x 4 mm, 0.5 mm pitch.

PTN5100D block diagram

PTN5100D block diagram

Why Used

  • Cooperatively works under the control of Policy controller MCU for power delivery negotiation and contract(s), Alternate mode and VDM exchanges
  • Back current protection on all pins when PTN5100D is unpowered
  • Provides dedicated IO pin (CC_ORIENT) for indicating Cable/plug orientation
  • Operating temperature -20 °C to 105 °C
  • ESD 8 kV HBM, 1 kV CDM

Where Used

  • Docking
  • Mobile Monitors
  • Multi-function Monitors
  • Portable/External Hard drives
  • Dongles

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Automotive tiny Real-Time Clock/calendar with alarm function and I²C-bus

Optimized for low power consumption, the PCA85063A is a CMOS Real-Time Clock and calendar that has an offset register which allows fine-tuning of the clock. All addresses and data are transferred serially via the two-line bidirectional I2C-bus. The maximum data rate of this RTC is 400 kbit/s.

The PCA85063A contains 18 8-bit registers with an auto-incrementing register address, an on-chip 32.768 kHz oscillator with integrated capacitors, a frequency divider which provides the source clock for the Real-Time Clock (RTC) and calender, and an I2C-bus interface with a maximum data rate of 400 kbit/s. The built-in address register will increment automatically after each read or write of a data byte up to the register 11h. After register 11h, the auto-incrementing will wrap around to address 00h.

Block diagram of PCA85063A

Block diagram of PCA85063A

Why Used

  • AEC-Q100 grade 2 compliant for automotive applications
  • Provides year, month, day, weekday, hours, minutes, and seconds based on a 32.768 kHz quartz crystal
  • Internal Power-On Reset (POR)
  • Oscillator stop detection function
  • Programmable offset register for frequency adjustment

Where Used

  • Tracking time of the day
  • Dashboard
  • Air condition
  • Telematics
  • Accurate timing

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Fm+ parallel bus to I2C-bus controller

Being able to operate as a master or a slave and a transmitter or receiver, the PCA9665/PCA9665A serves as an interface between most standard parallel-bus microcontrollers/microprocessors and the serial I2C-bus. It allows the parallel bus system to communicate bidirectionally with the I2C-bus. Communication with the I2C-bus is carried out on a Byte or Buffered mode using interrupt or polled handshake.

The PCA9665/PCA9665A contains eleven registers which are used to configure the operation of the device as well as to send and receive serial data. There are four registers that can be accessed directly and seven registers that are accessed indirectly by setting a register pointer.

Block diagram of PCA9665/PCA9665A

Block diagram of PCA9665/PCA9665A

Why Used

  • Multi-master capability
  • Internal oscillator trimmed to 15 % accuracy reduces external components
  • Software reset on parallel bus
  • Standard-mode and Fast-mode I²C-bus capable and compatible with SMBus
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

Where Used

  • Add I²C-bus port to controllers/processors that do not have one
  • Add additional I²C-bus ports to controllers/processors that need multiple I²C-bus ports
  • Converts 8 bits of parallel data to serial data stream to prevent having to run a large number of traces across the entire printed-circuit board

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8-bit A/D and D/A converter

Having four analog inputs, one analog output and a serial I²C‑bus interface, the PCF8591 is a single-chip, single-supply low-power 8-bit CMOS data acquisition device. Addess, control and data to and from the device are transferred serially via the two-line bidirectional I²C‑bus. This device can be used in analog input multiplexing, on-chip track and hold function, 8-bit analog-to-digital conversion and an 8-bit digital-to-analog conversion.

Each PCF8591 device in an I²C‑bus system is activated by sending a valid address to the device. The address consists of a fixed part and a programmable part. The programmable part must be set according to the address pins A0, A1 and A2. The address is always sent as the first byte after the start condition in the I2C-bus protocol.

Block Diagram

Block Diagram

Why Used

  • Single power supply
  • Operating supply voltage 2.5 V to 6.0 V
  • Max sampling rate given by I²C-bus speed
  • 4 analog inputs configurable as single ended or differential inputs
  • On-chip track and hold circuit

Where Used

  • Supply monitoring
  • Reference setting
  • Analog control loops

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DDR memory module temp sensor with integrated SPD

Mounted on a DDR3 Dual In-Line Memory Module (DIMM), SE97B measures temperature from -40 °C to +125 °C with JEDEC Grade B ±1 °C maximum accuracy between +75 °C and +95 °C critical zone and also provide 256 bytes of EEPROM memory communicating via the I2C-bus/SMBus. The SE97B thermal sensor and EEPROM operates over the VDD range of 3.0 V to 3.6 V.

To ensure higher reliability, SE97B incorporates a single die for both the temp sensor and EEPROM. The SMBus TIMEOUT function is supported to prevent system lock-ups. Manufacturer and Device ID registers provide the ability to confirm the identity of the device. Three address pins allow up to eight devices to be controlled on a single bus.

Block Diagram

Block Diagram

Why Used

  • Shutdown current: 0.1 µA (typ.) and 5.0 µA (max.)
  • ESD protection exceeds 2500 V HBM per JESD22-A114, 250 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
  • Available in HWSON8 package
  • 2-wire interface: I2C-bus/SMBus compatible, 0 Hz to 400 kHz

Where Used

  • DDR2 and DDR3 memory modules
  • Laptops, personal computers and servers
  • Enterprise networking
  • Hard disk drives and other PC peripherals

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