Monthly Archives: November 2016

ESD protection for ultra high-speed interfaces

Having six high-level ESD protection diode structures, PUSB3AB6 is a device designed to protect high-speed interfaces. These interfaces include SuperSpeed and Hi-SPeed USB combination, Secure Digital (SD) card 3.0 and Thunderbolt interfaces against ElectroStatic Discharge (ESD).

The device is encapsulated in a leadless ultra small DFN2111-7 9SOT1358-1) Surface-Mounted Device (SMD) plastic package. All signal lines are protected by a special diode configuration offering snapback ultra low line capacitance of only 0.15 pF.

Reflow Soldering Footprint

Reflow Soldering Footprint

Why Used

  • Line capacitance of only 0.15 pF for each channel
  • All signal lines with integrated rail-to-rail clamping diodes for downstream ESD protection of ±15 kV exceeding IEC 61000-4-2, level 4
  • Matched 0.5 mm trace spacing
  • Design-friendly pass-through signal routing

Where Used

  • Portable and wearable devices
  • Smartphones, tablet computers
  • TVs and monitors
  • DVD recorders and players
  • Notebooks, main board graphic cards and ports
  • set-top boxes and game consoles

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22-bit bi-directional low voltage translator

The GTL2000DGG is a 22-bit bi-directional low voltage translator that provides 22 NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference transistor (SREF and DREF). The voltage translations are between 1.0 V and 5.0 V without use of a direction pin.

When the Sn or Dn port is low the clamp is in the ON-state and a low resistance connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is high, the voltage on the Sn port is limited to the voltage set by the reference transistor (SREF). When the Sn port is high, the Dn port is pulled to VCC by the pull up resistors.

Typical Bi-Directional Voltage Translation

Typical Bi-Directional Voltage Translation

Why Used

  • Allows voltage level translation between 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5 V busses which allows direct interface with GTL, GTL+, LVTTL/TTL and 5 V CMOS levels
  • Low 6.5 Ω RDSON resistance between input and output pins (Sn/Dn)
  • No power supply required – Will not latch up
  • Flow-through pinout for ease of printed circuit board trace routing
  • ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V per JESD22-C101

Where Used

  • Any application that requires bi-directional or unidirectional voltage level translation from any voltage between 1.0 V and 5.0 V to any voltage between 1.0 V and 5.0 V
  • The open drain construction with no direction pin is ideal for bi-directional low voltage (e.g., 1.0 V, 1.2 V, 1.5 V, or 1.8 V) processor I²C port translation to the normal 3.3 V and/or 5.0 V I²C bus signal levels or GTL/GTL+ translation to LVTTL/TTL signal levels.

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Secure authentication microcontroller

Featuring a significantly enhanced secure microcontroller architecture, the A710x family is an MCU family that uses a dedicated security hardened MX51CPU. Extended instructions for Java and C code, linear addressing and high speed at low power are among many improvements added to the classic 80C51 core architecture.

The A710x family security concept is combining a comprehensive portfolio of NXP Semiconductors security measures which is protecting the chip against all types of attacks. The Triple-DES coprocessor provides a high level of leak-resistance to 1st order DPA, thus equally well resilient against all kinds of leakage attacks.

A710x family block diagram

A710x family block diagram

Why Used

  • Public Key Cryptography (PKC) coprocessor supporting RSA, Elgamal, DSS, Diffie-Hellman, Guillou-Quisquater, Fiat-Shamir and Elliptic Curves
  • High-speed AES coprocessor (128-bit parallel processing AES engine)
  • Low-power design using NXP®Semiconductors’ handshaking technology
  • 10 μA maximal deep sleep mode current with I²C pads operated in tristate mode, don’t obstructing the bus lines

Where Used

  • Embedded security
  • Counterfeit protection of hardware and software
  • Profile of service
  • Device identity

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Digital temperature sensor and thermal watchdog

Providing an overtemperature detection output, the LM75A is a temperature-to-digital converter using an on-chip band gap temperature sensor and Sigma-delta A-to-D conversion technique. It contains a number of data registers: Configuration register (Conf) to store the device settings such as device operation mode, OS operation mode, OS polarity and OS fault queue; temperature register (Temp) to store the digital temp reading, and set-point registers (Tos and Thyst) to store programmable overtemperature shutdown and hysteresis limits.

The device is powered-up in normal operation mode with the OS in comparator mode, temperature threshold of 80 Cel and hysteresis of 75 Cel, so that it can be used as a strand-alone thermostat with those pre-defined temperature set points.

Block Diagram

Block Diagram

Why Used

  • Pin-for-pin replacement for industry standard LM75 and offers improved temperature resolution of 0.125 Cel and specification of a single part over power supply range from 2.8 V to 5.5 V
  • Supply current of 3.5 uA in shutdown mode for power conservation
  • ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

Where Used

  • System thermal management
  • Personal computers
  • Electronics equipment
  • Industrial controllers

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Single-channel common-mode filter with integrated ESD protection network

Integrating two ultra-low capacitance rail-to-rail diodes, IP3319CX6 can eliminate efficiently common-mode noise from USB 2.0 and other high-speed interfaces with differential lines. This device has 2-lines (one differential channel) common-mode filter with integrated ESD protection  up to 15 kV contact discharge, exceeding IEC 61000-4-2, level 4.

IP3319CX6 is designed to protect sensitive I/Os, such as USB 2.0, Ethernet, Digital Video Interface (DVI) and Low-Voltage Differential Signaling (LVDS) interfaces from destruction by ElectroStatic Discharge (ESD). Due to the rail-to-rail concept, the protection is working independently from availability of a supply voltage.

Functional Diagram

Functional Diagram

Why Used

  • 2-lines (one differential mode) common-mode filter
  • ESD protection for the USB ID line
  • Extremely low clamping voltage
  • ESD protection up to ±15 kV on external contact pins
  • Ultra low ESD diode capacitance
  • WLCSP6 with 0.4 mm pitch

Where Used

  • USN 2.0 High-speed lines
  • LVDS interfaces
  • DVI

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