Monthly Archives: October 2016

64kB flash, 12kB SRAM, HVQFN32 package

Offering performance, low power, simple instruction set and memory addressing together with reduced code size, the LPC11U35FHI33 is an ARM Cortex-M0 based, low-cost 32-bit MCU designed for 8/16-bit microcontroller applications. It operates at CPU frequencies of up to 50 MHz.

The peripheral complement of the LPC11U35FHI33 includes up to 128 kB of flash memory, up to 12 kB of SRAM data memory and 4 kB EEPROM, one Fast-mode Plus I2C-bus interface, one RS-485/EIA-485 USART with support for synchronous mode and smart card interface, two SSP interfaces, four general purpose counter/timers, a 10-bit ADC, and up to 54 general purpose I/O pins.

Block Diagram

Block Diagram

Why Used

  • Non Maskable Interrupt (NMI) input selectable from several input sources
  • In-System Programming (ISP) and In-Application Programming (IAP)
  • ROM-based USB drivers. Flash updates via USB supported
  • High-current source output driver (20 mA) on one pin
  • Unique device serial number for identification

Where Used

  • Consumer peripherals
  • Medical
  • industrial control
  • Handheld scanners
  • USB audio devices

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Quad DSI 2.02 Master, Differential Drive, Freq Spread

Having enhanced bus fault performance, the 33781 is a master device for four differential DSI 2.02 buses. It contains the logic to interface the buses to a standard serial peripheral interface (SPI) port and the analog circuitry to drive data and power over the bus, and will receive data from the remote slave devices.

Independent frequency spreading for each channel further reduces interference by spreading the energy across many frequencies, reducing the energy in any single frequency. The device has enhanced register set with addressable buffer allows queuing of 4 independent slave commands at one time for each channel.

Simplified Application Diagram

Simplified Application Diagram

Why Used

  • Enhanced bus fault performance
  • Automatic message cyclical redundancy checking (CRC) generation and checking for each channel
  • Pseudo bus switch feature on channel 0
  • 8- to 16-Bit messages with 0- to 8-Bit CRC

Where Used

  • 77 GHz Radar System
  • Acceleration Sensors
  • Pressure Sensors

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Logic controlled high-side power switch

Used in power domain isolation applications to protect from out of range operation, the NX5P2090 is an advanced power switch for USB OTG applications. It includes under-voltage and over-voltage lockout, over-current, over-temperature, reverse bias and in-rush current protection circuits. The device is designed to automatically isolate a VBUS OTG voltage source from a VBUS interface pin when a fault occurs.

NX5P2090 features two power switch terminals, one input (VINT) and one output (VBUS); a current limit input (ILIM) for defining the over current and in-rush current limit; a voltage detect output (VDET) to monitor the voltage level on VBUS; an open-drain fault output (FAULT) to indicate when a fault condition has occurred and an enable input (EN) to control the state of the switch. This device os designed for operation from 3 V to 5.5 V.

Logic Diagram (Simplified Schematic)

Logic Diagram (Simplified Schematic)

Why Used

  • 30 V tolerant on VBUS
  • Very low ON resistance: 100 mΩ (maximum) at a supply voltage of 4.0 V
  • Low-power mode (ground current 20 μA typical)
  • Soft start turn-on slew rate
  • Specified from -40 °C to +85 °C

Where Used

  • USB OTG applications

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Dual IC card interface

Controlled by the I²C-bus, the TDA8020HL is a one-chip dual smart card interface. It guarantees conformity to ISO 7816 or EMV2000 with very few external components. TDA8020HL operates with a supply voltage from 2.7 to 6.5 V. An integrated voltage supervisor ensures that no spike appears on cards contacts during power-on or off.

The TDA8020HL operates in standard mode (100 kHz clock rate) and fast mode (400 kHz clock rate) defined in the I2C-bus specification. This card interface has automatic activation and deactivation sequences by means of integrated sequences, as well as automatic clock count and reset toggling during warm or cold reset.

Block Diagram

Block Diagram

Why Used

  • Two independent 6 contacts smart card interfaces
  • Integrated DC-to-DC converter (doubler, tripler or follower) for allowing power supply from 2.7 to 6.5 V
  • Four possible devices in parallel due to two I²C-bus address pins
  • 6 kV ESD protection on cards contacts
  • Current limitation on pins CLK, RST, I/O and VCC

Where Used

  • Set top boxes
  • Banking terminals
  • Internet terminals

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