Monthly Archives: August 2016

MIFARE SAM AV2 or AV2.6, HVQFN32 package

Supporting TDEA, AES and RSA capabilities, the NXP MIFARE SAM AV2 hardware solution is the ideal add-on for reader devices offering additional security services. It offers secure storage and secure communication in a variety of infrastructures.

MIFARE SAM AV2 provides a significant boost in performance to the reader along with faster communication between reader and module when used in combination with a reader IC supporting innovative “X” features. The connection between the SAM and the reader is performed using security protocols based on either symmetric cryptography (TDEA and AES) or PKI RSA asymmetric cryptography.

Block Diagram

Block Diagram

Why Used

  • Supports MIFARE Crypto1, TDEA (Triple DES encryption algorithm), RSA and AES cryptography
  • Secure storage and updating of keys (key usage counters)
  • Secure Host to SAM and back end to SAM communication with RSA based cryptography
  • Support for DESFire and MIFARE Plus authentication (with related secure messaging and session key generation)

Where Used

  • Access management
  • Public transport
  • Loyalty programs
  • Micro payment

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USB Type-C High performance Crossbar Switch IC

Meant to be used for Type-C connector interface high speed passive switching applications, CBTL08GP053 is an USB Type-C High Performance Crossbar Switch IC which provides switching of high speed differential signals that correspond to various interface standards: USB3.1 (10 Gbps), DP1.3 (8.1 Gbps), PCI Express 3.0 (8 Gbps), etc.

CBTL08GP053 operates from a single platform power supply VDD and provides the I²C-bus interface for switch control, configuration and status update. Available in a small footprint package option: VFBGA40 4.75 mm x 3.25 mm, 0.5 mm pitch, this IC is targeted for a wide range of platforms (PCs, Tablets, Convertibles, Smart phones) and PC Accessories (e.g. Docks, Monitors, etc.) applications.

Functional Block Diagram

Functional Block Diagram

Why Used

  • Performs Multiplexing or Switching of High speed differential signals or Single ended signals
  • All switches are direction agnostic
  • Design based on both Patented and Patent pending High performance Switch technology
  • Very low propagation delay (80 ps typical) and inter pair skew (35 ps typical)
  • Supports I²C slave interface Standard mode (100 kbit/s) and Fast mode (400 kbit/s)
  • Back current protection on Control pins and exposed connector side I/O pins

Where Used

  • PC platforms: Notebook PCs, Desktop PCs, Ultrabooks
  • Tablets, 2:1 Convertibles, Smartphones and Portable devices
  • PC accessories/peripherals: Multi-Function Monitors, etc.

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I²C-bus Fm+, 1 degree C accuracy, digital temperature sensor and thermal watchdog

Featuring ±1 °C accuracy over ‑25 °C to +100 °C range, the PCT2075 is a temperature-to-digital converter that uses an on-chip band gap temperature sensor and Sigma-Delta A‑to‑D conversion technique with an overtemperature detection output that is a drop-in replacement for other LM75 series thermal sensors. It includes an open-drain output (OS) which becomes active when the temperature exceeds the programmed limits.

The PCT2075 is capable of being configured for different operation conditions. It can be set in normal mode to periodically monitor the ambient temperature, or in shut-down mode to minimize power consumption. It can be used as a stand-alone thermostat with those pre-defined temperature set points.

Block diagram of PCT2075

Block diagram of PCT2075

Why Used

  • 1 MHz Fast-mode Plus 30 mA SDA drive allows more devices on the same bus but is backward compatible to Fast-mode and Standard-mode
  • Programmable temperature threshold and hysteresis set points during operation
  • Stand-alone operation as thermostat at power-up
  • ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

Where Used

  • System thermal management
  • Personal computers
  • Electronics equipment
  • Industrial controllers

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2-bit Bidirectional Low Voltage Translator

The Gunning Transceiver Logic – Transceiver Voltage Clamps (GTL-TVC) provide high-speed voltage translation with low ON-state resistance and minimal propagation delay. The GTL2002 provides 2 NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference transistor (SREF and DREF). The device allows bidirectional voltage translations between 1.0 V and 5.0 V without use of a direction pin.

When the Sn or Dn port is LOW the clamp is in the ON-state and a low resistance connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is HIGH, the voltage on the Sn port is limited to the voltage set by the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to VCCby the pull-up resistors. This functionality allows a seamless translation between higher and lower voltages selected by the user, without the need for directional control.

Product Block Diagram

Product Block Diagram

Why Used?

  • Allows voltage level translation between 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5 V buses, which allows direct interface with GTL, GTL+, LVTTL/TTL and 5 V CMOS levels
  • Provides bidirectional voltage translation with no direction pin
  • Low 6.5 Ω ON-state resistance (Ron) between input and output pins (Sn/Dn)
  • No power supply required; will not latch up
  • Low standby current

Where Used?

  • Any application that requires bidirectional or unidirectional voltage level translation from any voltage between 1.0 V and 5.0 V to any voltage between 1.0 V and 5.0 V
  • The open-drain construction with no direction pin is ideal for bidirectional low voltage (e.g., 1.0 V, 1.2 V, 1.5 V, or 1.8 V) processor I²C-bus port translation to the normal 3.3 V or 5.0 V I²C-bus signal levels or GTL/GTL+ translation to LVTTL/TTL signal levels

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8-channel I2C-bus multiplexer with reset

Allowing immediate communication between the master and downstream devices, the PCA9547 powers up with Channel 0 connected. An active LOW reset input allows the PCA9547 to recover from a situation where one of the downstream I²C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the I²C-bus state machine causing all the channels to be deselected, except Channel 0 so that the master can regain control of the bus.

It is an octal bidirectional translating multiplexer controlled by the I²C-bus. The SCL/SDA upstream pair fans out to eight downstream pairs, or channels but only one SCx/SDx channel can be selected at a time, determined by the contents of the programmable control register.

Product Block Diagram

Product Block Diagram

Why Used

  • Operating power supply voltage range of 2.3 V to 5.5 V
  • 5 V tolerant inputs
  • 0 Hz to 400 kHz clock frequency
  • ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

Where Used

  • Basestation – discretes focus / transceiver board
  • Digital media adapters
  • LCD display – discretes focus
  • PCI analog / DVB-T stereo TV receiver
  • UMA-enabled GSM/GPRS/EDGE VAS Phone (6100)

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