2-channel I2C-Bus Master Arbiter

Block Diagram of PCA9641

Block Diagram of PCA9641

A 2-channel I2C-bus master arbiter IC is a 2-to-1 I2C master demultiplexer with an arbiter function device, which is the PCA9641. This PCA9641 is designed for high reliability dual master I2C-bus applications where correct system operation is required, even when two I2C-bus masters issue commands at the same time.

The arbiter will select a winner and let it work uninterrupted, and the losing master will take control of the I2C-bus after the winner has finished. The arbiter also allows for queued requrests where a master requests the downstream bus while the other master has control.

Why Used

  • Channel selection via I2C-bus
  • Arbitration active when two masters try to take the downstream I2C-bus at the same time
  • 2 active LOW interrupt outputs to master controllers
  • Four address pins allowing up to 112 different addresses
  • The winning master controls the downstream bus until it is done, as long as it is within the reserve time

Where Used

  • High reliability systems with dual masters
  • Gatekeeper multiplexer on long single bus
  • Bus initialization/recovery for slave devices without hardware reset
  • Allow masters without arbitration logic to share resources

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