10-bit bidirectional low voltage translator

Allowing bidirectional voltage translations between 1.0 V and 5.0 V without use of a direction pin, the GTL2010 provides 10 NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference transistor (SREF and DREF). When the Sn or Dn port is LOW, the clamp is in the ON-state and a low resistance connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is HIGH the voltage on the Sn port is limited to the voltage set by the reference transistor (SREF).

All transistors have the same electrical characteristics and there is minimal deviation from one output to another in voltage or propagation delay. This is a benefit over discrete transistor voltage translation solutions, since the fabrication of the transistors is symmetrical.

Block diagram: GTL2000DGG, GTL2000DL, GTL2010BS, GTL2010PW

Block diagram: GTL2000DGG, GTL2000DL, GTL2010BS, GTL2010PW

Why Used

  • Provides bidirectional voltage translation with no direction pin
  • Supports hot insertion
  • No power supply required: will not latch up
  • Low standby current
  • Flow-through pinout for ease of printed-circuit board trace routing

Where Used

  • Any application that requires bidirectional or unidirectional voltage level translation from any voltage from 1.0 V to 5.0 V to any voltage from 1.0 V to 5.0 V
  • The open-drain construction with no direction pin is ideal for bidirectional low voltage (for example, 1.0 V, 1.2 V, 1.5 V or 1.8 V) processor I²C-bus port translation to the normal 3.3 V and/or 5.0 V I²C-bus signal levels or GTL/GTL+ translation to LVTTL/TTL signal levels

Read more…